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Si41 33G Si412 3G/22G/13G/12G
D U A L -B A N D R F S Y N T H E S I Z E R WI T H I N T E G R A T E D V C O S F O R G S M A N D G P R S WI R E L E S S C O M M U N I C A T I O N S
Features
" "
RF1: 900 MHz to 1.8 GHz RF2: 750 MHz to 1.5 GHz IF: 500 MHz to 1000 MHz
! ! !
! ! !
IF Synthesizer
"
Integrated VCOs, Loop Filters, ! ! Varactors, and Resonators Minimal External Components Required
Applications
Pin Assignments
!
GSM, DCS1800, and PCS1900 Cellular Telephones
! !
GPRS Data Terminals HSCSD Data Terminals
S C LK S D ATA
S i4 1
!
33
Ordering Information: See page 28.
Description
The SI4133G is a monolithic integrated circuit that performs both IF and dual-band RF synthesis for GSM and GPRS wireless communications applications. The SI4133G includes three VCOs, loop filters, reference and VCO dividers, and phase detectors. Divider and power down settings are programmable through a three-wire serial interface.
G -B T
!
Dual-Band RF Synthesizers
!
Fast Settling Time: 140 s Low Phase Noise Programmable Power Down Modes 1 A Standby Current 18 mA Typical Supply Current 2.7 V to 3.6 V Operation Packages: 24-Pin TSSOP and 28-Pin MLP
SI4133G-BT
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
SENB VDDI IF O U T GNDI IF L B IF L A GNDD VDDD GNDD X IN PW DNB AUXOUT
GNDR R FL D R FL C GNDR R FL B
Functional Block Diagram
R efe re nce A m p lifier P ow er D ow n C ontrol
R FL A GNDR GNDR
X IN
/ 65
P hase D etector R F1
R FL A R FL B
R FO U T VDDR
P W DN B
/N
R FO U T
S DA TA S CL K S EN B
SDATA
IFOUT
23
GNDR
SENB
SCLK
R FL D R F2
22-b it D ata R egister
/N
GNDR
1 2 3 4 5 6 7
28
27
26
25
24
22 21 20 19 18 17 16 15
GNDI
VDD I
S erial Interfa ce
P hase D etector
R FL C
SI4133G-BM
GNDI IF L B IF L A GNDD VDDD GNDD X IN
A UX O U T
Test Mux
P hase D etector IF
IFO UT
R FLD R FLC
/N
IFL A IFL B
GNDR R FLB R FLA GNDR
8
9
10
11
12
13
14
RFOU T
AUX OU T
GNDR
GNDR
VDDR
PW DNB
Patents pending
Rev. 1.1 4/01 Copyright (c) 2001 by Silicon Laboratories SI4133G-DS11
GNDD
S i4 13 3G
2
Rev. 1.1
SI4133G TA B L E O F CON T E N T S
Section
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF and IF Outputs (RFOUT and IFOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: SI4133G-BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: SI4133G-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SI4133G Derivative Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline: SI4133G-BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline: SI4133G-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Page
4 15 15 15 16 17 17 17 18 18 18 20 24 26 28 28 29 30 32
Rev. 1.1
3
S i4 13 3G
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Ambient Temperature Supply Voltage Supply Voltages Difference Symbol TA VDD V (VDDR - VDDD), (VDDI - VDDD) Test Condition Min -20 2.7 -0.3 Typ 25 3.0 -- Max 85 3.6 0.3 Unit C V V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at 3.0 V and an operating temperature of 25C unless otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter DC Supply Voltage Input Current3 Input Voltage3 Storage Temperature Range Symbol VDD IIN VIN TSTG Value -0.5 to 4.0 10 -0.3 to VDD+0.3 -55 to 150 Unit V mA V
o
C
Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This device is a high performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of this device should only be done at ESD-protected workstations. 3. For signals SCLK, SDATA, SENB, PWDNB and XIN.
4
Rev. 1.1
SI4133G
Table 3. DC Characteristics
(VDD = 2.7 to 3.6 V, TA = -20 to 85C
Parameter Typical Supply Current
1
Symbol
Test Condition RF1 and IF Operating
Min -- -- -- --
Typ 18 13 12 10 1 -- -- -- -- -- --
Max 31 17 17 14 -- -- 0.3 VDD 10 10 -- 0.4
Unit mA mA mA mA A V V A A V V
RF1 Mode Supply Current1 RF2 Mode Supply Current1 IF Mode Supply Current1 Standby Current High Level Input Voltage2 Low Level Input Voltage2 High Level Input Current2 Low Level Input Current2 High Level Output Voltage3 Low Level Output Voltage3 VIH VIL IIH IIL VOH VOL VIH = 3.6 V, VDD = 3.6 V VIL = 0 V, VDD= 3.6 V IOH = -500 A IOH = 500 A PWDNB = 0
-- 0.7 VDD -- -10 -10 VDD-0.4 --
Notes: 1. RF1 = 1.55 GHz, RF2 = 1.2 GHz, IF = 800 MHz 2. For signals SCLK, SDATA, SENB, and PWDNB. 3. For signal AUXOUT.
Rev. 1.1
5
S i4 13 3G
Table 4. Serial Interface Timing
(VDD = 2.7 to 3.6 V, TA = -20 to 85C)
Parameter1 SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time SDATA Setup Time to SCLK2 SDATA Hold Time from SCLK2 SENB to SCLK Delay Time
2
Symbol tclk tr tf th tl tsu thold ten1 ten2 ten3 tw
Test Condition Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2
Min 40 -- -- 10 10 5 0 10 12 12 10
Typ -- -- -- -- -- -- -- -- -- -- --
Max -- 50 50 -- -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns
SCLK to SENB Delay Time2 SENB to SCLK Delay Time2 SENB Pulse Width
Notes: 1. All timing is referenced to the 50% level of the waveform, unless otherwise noted. 2. Timing is not referenced to 50% level of waveform. See Figure 2.
tr
80%
tf
S CLK
50% 20%
th
t clk
tl
Figure 1. SCLK Timing Diagram
6
Rev. 1.1
SI4133G
ts u
thold
S CLK
S DA TA
D17
D16
D15
A1
A0 ten3 ten2
ten1
S E NB
tw
Figure 2. Serial Interface Timing Diagram
First bit c loc ked in
Las t bit c loc ked in
DDDDDDDDD 17 16 15 14 13 12 11 10 9
D 8
D 7
D 6
DD 54
D 3
D 2
D 1
D 0
A 3
A 2
A 1
A 0
data field
addres s field
Figure 3. Serial Word Format
Rev. 1.1
7
S i4 13 3G
Table 5. RF and IF Synthesizer Characteristics
(VDD = 2.7 to 3.6 V, TA = -20 to 85C)
Parameter1 XIN Input Frequency Reference Amplifier Sensitivity Phase Detector Update Frequency RF1 Center Frequency Range RF2 Center Frequency Range IF VCO Center Frequency Tuning Range from fCEN RF1 VCO Pushing RF2 VCO Pushing IF VCO Pushing RF1 VCO Pulling RF2 VCO Pulling IF VCO Pulling RF1 Phase Noise RF1 Integrated Phase Error RF2 Phase Noise RF2 Integrated Phase Error IF Phase Noise IF Integrated Phase Error RF1 Harmonic Suppression RF2 Harmonic Suppression IF Harmonic Suppression RFOUT Power Level IFOUT Power Level RF1 Reference Spurs
Symbol fREF VREF f fCEN fCEN fCEN
Test Condition
Min -- 0.5
Typ 13 -- 200 -- -- -- -- 0.5 0.4 0.3 0.4 0.1 0.1 -132 -142 0.9 -134 -144 0.7 -117 0.4 -26 -26 -26 -2 -6 -70 -75 -80 -75 -80 -80 140 --
Max -- VDD +0.3 1720 1429 952 5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -1 -- -- -- -- -- -- -- 100
Unit MHz VPP KHz MHz MHz MHz % MHz/V MHz/V MHz/V MHzPP MHzPP MHzPP dBc/Hz dBc/Hz deg rms dBc/Hz dBc/Hz deg rms dBc/Hz deg rms dBc dBc dBc dBm dBm dBc dBc dBc dBc dBc dBc s ns
f = fREF/R 947 789 526 -5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -7 -8 -- -- -- -- -- -- -- --
Note: LEXT 10% Open loop
VSWR = 2:1, all phases, open loop 1 MHz offset 3 MHz offset 100 Hz to 100 kHz 1 MHz offset 3 MHz offset 100 Hz to 100 kHz 100 kHz offset 100 Hz to 100 kHz Second Harmonic
ZL = 50 ZL = 50
RF2 Reference Spurs
Power Up Request to Synthesizer Ready Time, RF1, RF2, IF2 Power Down Request to Synthesizer Off Time3
tpup tpdn
Offset = 200 kHz Offset = 400 kHz Offset = 600 kHz Offset = 200 kHz Offset = 400 kHz Offset = 600 kHz Figures 4, 5 Figures 4, 5
Notes: 1. RF1 = 1.55 GHz, RF2 = 1.2 GHz, IF = 550 MHz for all parameters unless otherwise noted. 2. From power up request (PWDNB or SENB during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is 120 s. 3. From power down request (PWDNB, or SENB during a write of 0 to bits PDIB and PDRB in Register 2) to supply current equal to IPWDN.
8
Rev. 1.1
SI4133G
RF and IF s y nthes iz ers s ettled to w ithin 0.1 ppm f requenc y error.
R F and IF synthesizers s ettled to within 0.1 ppm frequency error.
t
IT I PW D N
p up
t
p dn
IT I PW D N
t pup
t pdn
S E NB
PW DNB
S DA TA
PD IB = 1 PD R B = 1
PD IB = 0 PD R B = 0
Figure 4. Software Power Management Timing Diagram
Figure 5. Hardware Power Management Timing Diagram
Rev. 1.1
9
S i4 13 3G
TRACE A: Ch1 FM Gate Time A Offset 800 Hz
133.59375
us
Real Axis is 0.1 ppm/div
160 Hz /div
-800 Hz Start: 0 s Stop: 299.21875 us
Figure 6. Typical Transient Response RF1 at 1.6 GHz with 200 kHz Phase Detector Update Frequency
10
Rev. 1.1
SI4133G
-60
-70
-80
Phase Noise (dBc/Hz)
-90
-100
-110
-120
-130
-140 2 10
10
3
10 Offset Frequency (Hz)
4
10
5
10
6
Figure 7. Typical RF1 Phase Noise at 1.6 GHz with 200 kHz Phase Detector Update Frequency
Figure 8. Typical RF1 Spurious Response at 1.6 GHz with 200 kHz Phase Detector Update Frequency
Rev. 1.1
11
S i4 13 3G
-60
-70
-80
Phase Noise (dBc/Hz)
-90
-100
-110
-120
-130
-140 2 10
10
3
10 Offset Frequency (Hz)
4
10
5
10
6
Figure 9. Typical RF2 Phase Noise at 1.2 GHz with 200 kHz Phase Detector Update Frequency
Figure 10. Typical RF2 Spurious Response at 1.2 GHz with 200 kHz Phase Detector Update Frequency
12
Rev. 1.1
SI4133G
-70
-80
-90
Phase Noise (dBc/Hz)
-100
-110
-120
-130
-140
-150 2 10
10
3
10 Offset Frequency (Hz)
4
10
5
10
6
Figure 11. Typical IF Phase Noise at 550 MHz with 200 kHz Phase Detector Update Frequency
Figure 12. IF Spurious Response at 550 MHz with 200 kHz Phase Detector Update Frequency
Rev. 1.1
13
S i4 13 3G
S i41 33 G -B T
From S ys te m C on tro lle r
1 2
S C LK S D ATA
SENB VDDI IFO U T GNDI IFL B IFL A GNDD VDDD GNDD X IN PW DNB AUXO UT
24
VDD
23
0 .02 2 F 1 0 nH 5 6 0p F IFO U T
3
22 21 20 19 18
GNDR
4 5
R FL D R FL C
P rinte d Tra c e Ind uc tors
6
P rinte d Tra c e Ind uc tor or C hip In du ctor
GNDR
7 8
R FL B R FL A
V DD
17 16
0 .02 2 F
9 10
GNDR GNDR
560 pF
15 14 13
E x te rn al C loc k PDWNB AUXO UT
5 6 0p F R FO U T
2 nH
11
R FO U T
0.022 F
V DD
12
VDDR
Figure 13. Typical Application Circuit: SI4133G-BT
F ro m S ys tem C o n tro ller
28 27 26 25
VDD
0.02 2 F 10 n H 56 0p F IF O U T
24 23 22
SENB
SDATA
IFOUT
GNDR
SCLK
GNDI
VDDI
1 2 3
GNDR RFLD RFLC GNDR RFLB RFLA GNDR
GNDI IF L B IF L A
21 20 19 18 17 16 15
P rin ted Trace In d u cto r o r C h ip In d u cto r
P rin ted Trace In d u cto rs
4 5 6 7
S i4 1 3 3 G -B M
GNDD VDDD GNDD
V DD
0.02 2 F 56 0p F
AUXOUT
PWDNB
RFOUT
X IN
E xte rn a l C lo ck
GNDR
GNDR
8
9
10
11
12
13
14
V DD
0.02 2 F AUXOUT PW DNB 2n H 56 0p F RFOUT
Figure 14. Typical Application Circuit: SI4133G-BM
14
Rev. 1.1
GNDD
VDDR
SI4133G
Functional Description
The SI4133G is a monolithic integrated circuit that performs IF and dual-band RF synthesis for many wireless applications such as GSM, DCS1800, and PCS1900. Its fast transient response also makes the SI4133G especially well suited to GPRS and HSCSD multislot applications where channel switching and settling times are critical. This integrated circuit (IC), with a minimum number of external components, is all that is necessary to implement the frequency synthesis function. The SI4133G has three complete phase-locked loops (PLLs) with integrated voltage-controlled oscillators (VCOs). The low phase noise of the VCOs makes the SI4133G suitable for use in demanding wireless communications applications. Also integrated are phase detectors, loop filters, and reference dividers. The IC is programmed through a three-wire serial interface. One PLL is provided for IF synthesis, and two PLLs are provided for dual-band RF synthesis. One RF VCO is optimized to have its center frequency set between 947 MHz and 1720 MHz, while the second RF VCO is optimized to have its center frequency set between 789 MHz and 1429 MHz. The IF VCO is optimized to have its center frequency set between 526 MHz and 952 MHz. Each PLL can adjust its output frequency by 5% relative to its VCO center frequency. The center frequency of each of the three VCOs is set by connection of an external inductance. Inaccuracies in the value of the inductance are compensated for by the SI4133G's proprietary self-tuning algorithm. This algorithm is initiated each time the PLL is powered-up (by either the PWDNB pin or by software) and/or each time a new output frequency is programmed. The two RF PLLs share a common output pin, so only one PLL is active at a given time. Because the two VCOs can be set to have widely separated center frequencies, the RF output can be programmed to service different frequency bands, thus making the SI4133G ideal for use in dual-band cellular handsets. The unique PLL architecture used in the SI4133G produces a transient response that is superior in speed to fractional-N architectures without suffering the high phase noise or spurious modulation effects often associated with those designs. The SI4133G is programmed serially with 22-bit words comprised of 18-bit data fields and 4-bit address fields. When the serial interface is enabled (i.e., when SENB is low) data and address bits on the SDATA pin are clocked into an internal shift register on the rising edge of SCLK. Data in the shift register is then transferred on the rising edge of SENB into the internal data register addressed in the address field. The serial interface is disabled when SENB is high. Table 10 on page 20 summarizes the data register functions and addresses. The internal shift register will ignore any leading bits before the 22 required bits.
Setting the VCO Center Frequencies
The PLLs can adjust the IF and RF output frequencies 5% with respect to their VCO center frequencies. Each center frequency is established by the value of an external inductance connected to the respective VCO. Manufacturing tolerances of 10% for the external inductances are acceptable. The SI4133G will compensate for inaccuracies in each inductance by executing a self-tuning algorithm following PLL powerup or following a change in the programmed output frequency. Because the total tank inductance is in the low nH range, the inductance of the package needs to be considered in determining the correct external inductance. The total inductance (LTOT) presented to each VCO is the sum of the external inductance (LEXT) and the package inductance (LPKG). Each VCO has a nominal capacitance (CNOM) in parallel with the total inductance, and the center frequency is as follows:
1 fCEN = --------------------------------------------2 L TOT C NOM
or
1 fCEN = ---------------------------------------------------------------------2 ( L PKG + L EXT ) C NOM
Tables 6 and 7 summarize these characteristics for each VCO.
Serial Interface
A timing diagram for the serial interface is shown in Figure 2 on page 7. Figure 3 on page 7 shows the format of the serial word.
Rev. 1.1
15
S i4 13 3G
Table 6. SI4133G-BT VCO Characteristics
VCO Fcen Range Cnom (MHz) (pF) Min Max Lpkg (nH) Lext Range (nH) Min Max
in addition to 2.3 nH of LPKG (SI4133G-BT), will present the correct total inductance to the VCO. In manufacturing, the external inductance can vary 10% of its nominal value and the SI4133G will correct for the variation with the self-tuning algorithm. In most cases, particularly for the RF VCOs, the requisite value of the external inductance is small enough to allow a PC board trace to be utilized. During initial board layout, a length of trace approximating the desired inductance can be used. For more information, please refer to Application Note 31.
RF1 RF2 IF
947 789 526
1720 1429 952
4.3 4.8 6.5
2.0 2.3 2.1
0.0 0.3 2.2
4.6 6.2 12.0
Self-Tuning Algorithm
Table 7. SI4133G-BM VCO Characteristics
VCO Fcen Range Cnom (MHz) (pF) Min Max Lpkg (nH) Lext Range (nH) Min Max
RF1 RF2 IF
947 789 526
1720 1429 952
4.3 4.8 6.5
1.5 1.5 1.6
0.5 1.1 2.7
5.1 7.0 12.5
The self-tuning algorithm is initiated immediately following power-up of a PLL or, if the PLL is already powered, following a change in its programmed output frequency. This algorithm attempts to tune the VCO so that its free-running frequency is near the desired output frequency. In so doing, the algorithm will compensate for manufacturing tolerance errors in the value of the external inductance connected to the VCO. It will also reduce the frequency error for which the PLL must correct to get the precise desired output frequency. The self-tuning algorithm will leave the VCO oscillating at a frequency in error by somewhat less than 1% of the desired output frequency. After self-tuning, the PLL controls the VCO oscillation frequency. The PLL will complete frequency locking, eliminating any remaining frequency error. Thereafter, it will maintain frequency-lock, compensating for effects caused by temperature and supply voltage variations.
L PK G 2 L EXT
L PK G 2
Figure 15. External Inductance Connection
As a design example, suppose it is desired to synthesize frequencies in a 25 MHz band between 1120 MHz and 1145 MHz. The center frequency should be defined as midway between the two extremes, or 1132.5 MHz. The PLL will be able to adjust the VCO output frequency 5% of the center frequency, or 56.6 MHz of 1132.5 MHz (i.e., from approximately 1076 MHz to 1189 MHz, more than enough for this example). The RF2 VCO has a CNOM of 4.8 pF, and a 4.1 nH inductance (correct to two digits) in parallel with this capacitance will yield the desired center frequency. An external inductance of 1.8 nH should be connected between RFLC and RFLD as shown in Figure 15. This,
The SI4133G's self-tuning algorithm will compensate for component value errors at any temperature within the specified temperature range. However, the ability of the PLL to compensate for drift in component values that occur after self-tuning is limited. For external inductances with temperature coefficients around 150 ppm/oC, the PLL will be able to maintain lock for changes in temperature of approximately 30oC. Applications where the PLL is regularly powered down (such as GSM) or switched between channels minimize or eliminate the potential effects of temperature drift because the VCO is re-tuned when it is powered up or when a new frequency is programmed. In applications where the ambient temperature can drift substantially after self-tuning, it may be necessary to monitor the LDETB (lock-detect bar) signal on the AUXOUT pin to determine the locking state of the PLL. (See "Auxiliary Output (AUXOUT)" on page 18 for how to select LDETB.) The LDETB signal is normally low after self-tuning is completed but will rise to a logic high condition when
16
Rev. 1.1
SI4133G
either the IF or RF PLL nears the limit of its compensation range (LDETB will also be high when either PLL is executing the self-tuning algorithm). The output frequency will still be locked when LDETB goes high, but the PLL will eventually lose lock if the temperature continues to drift in the same direction. Therefore, if LDETB goes high both the IF and RF PLLs should promptly be re-tuned by initiating the self-tuning algorithm. the RF and IF PLLs T = 5 S. During the first 6.5 update periods, the SI4133G executes the self-tuning algorithm. Thereafter the PLL controls the output frequency. Because of the unique architecture of the SI4133G PLLs, the time required to settle the output frequency to 0.1 ppm error is approximately 21 update periods. Thus, the total time after power-up or a change in programmed frequency until the synthesized frequency is well settled (including time for self-tuning) is around 28 update periods or 140 S.
Output Frequencies
The IF and RF output frequencies are set by programming the N-Divider registers. Each RF PLL has its own N register and can be programmed independently. All three PLL R dividers are fixed at R = 65 to yield a 200 kHz phase detector update rate from a 13 MHz reference frequency. Programming the N-Divider register for either RF1 or RF2 automatically selects the associated output. The reference frequency on the XIN pin is divided by R and this signal is the input to the PLL's phase detector. The other input to the phase detector is the PLL's VCO output frequency divided by N. The PLL works to make these frequencies equal. That is, after an initial transient
f OUT fREF ----------- = ----------N 65
RF and IF Outputs (RFOUT and IFOUT)
The RFOUT pin is driven by an amplifier that buffers the output pin from the RF VCOs, and must be coupled to its load through an AC coupling capacitor. The amplifier receives its input from either the RF1 or RF2 VCO, depending upon which N-Divider register was last written. For example, programming the N-Divider register for RF1 automatically selects the RF1 VCO output. A matching network is required to maximize power delivered into a 50 load. The network consists of a 2 nH series inductance, which may be realized with a PC board trace, connected between the RFOUT pin and the AC coupling capacitor. The network is made to provide an adequate match for both the RF1 and RF2 frequency bands, and also filters the output signal to reduce harmonic distortion. A 50 load is not required for proper operation of the SI4133G. Depending on transceiver requirements, the matching network may not be needed. See Figure 16.
560 pF RFOUT 2 nH 50
or
N f OUT = ----- f REF 65
For XIN = 13 MHz this simplifies to
fOUT = N 200 kHz
The integer N is set by programming the RF1 N-Divider register (Register 3), the RF2 N-Divider register (Register 4), and the IF N-Divider register (Register 5). Each N divider is implemented as a conventional high speed divider. That is, it consists of a dual-modulus prescaler, a swallow counter, and a lower speed synchronous counter. However, the calculation of these values is done automatically. Only the appropriate N value needs to be programmed.
Figure 16. RFOUT 50 Test Circuit
The IFOUT pin is driven by an amplifier that buffers the output pin from the IF VCO. The IFOUT pin must be coupled to its load through an AC coupling capacitor. A matching network is required to maximize power delivered into a 50 load. See Figure 17.
PLL Loop Dynamics
The transient response for each PLL has been optimized for a GSM application. VCO gain, phase detector gain, and loop filter characteristics are not programmable. The settling time for each PLL is directly proportional to its phase detector update period T (T equals 1/f). For a GSM application with a 13 MHz reference frequency,
Rev. 1.1
17
S i4 13 3G
Reference Frequency Amplifier
560 pF IFOUT L MATCH 50
The SI4133G provides a reference frequency amplifier. If the driving signal has CMOS levels it can be connected directly to the XIN pin. Otherwise, the reference frequency signal should be AC coupled to the XIN pin through a 560 pF capacitor.
Power Down Modes
Figure 17. IFOUT 50 Test Circuit Table 8. LMATCH Values
Frequency 500-600 MHz 600-800 MHz 800-1 GHz LMATCH 40 nH 27 nH 18 nH Table 9 summarizes the power down functionality. The SI4133G can be powered down by taking the PWDNB pin low or by setting bits in the Power Down register (Register 1). When the PWDNB pin is low, the SI4133G will be powered down regardless of the Power Down register settings. When the PWDNB pin is high, power management is under control of the Power Down register bits. The reference frequency amplifier, IF, and RF sections of the SI4133G circuitry can be individually powered down by setting the Power Down register bits PDIB and PDRB low, respectively. The reference frequency amplifier will also be powered up if either of the PDRB or PDIB bits are high. Also, setting the AUTOPDB bit to 1 in the Main Configuration register (Register 0) is equivalent to setting both bits in the Power Down register to 1. The serial interface remains available and can be written in all power down modes.
The IF output level is dependent upon the load. Figure 18 displays the output level versus load resistance for a variety of output frequencies.
450
400
350 LPWR=1 LPWR=0 300 Output Voltage (mVrms)
Auxiliary Output (AUXOUT)
The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register (Register 0). The LDETB signal can be selected by setting the AUXSEL bits to 11. As discussed previously, this signal can be used to indicate that the IF or RF PLL is about to lose lock due to excessive ambient temperature drift and should be re-tuned.
250
200
150
100
50
0 0 200 400 600 Load Resistance () 800 1000 1200
Figure 18. Typical IF Output Voltage vs. Load Resistance at 550 MHz
For resistive loads greater than 500 the output level saturates and the bias currents in the IF output amplifier are higher than they need be. The LPWR bit in the Main Configuration register (Register 0) can be set to 1 to reduce the bias currents and therefore reduce the power dissipated by the IF amplifier. For loads less than 500 LPWR should be set to 0 to maximize the output level.
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Rev. 1.1
SI4133G
Table 9. Power Down Configuration
PWDNB Pin AUTOPDB PDIB PDRB IF Circuitry RF Circuitry
PWDNB = 0
x 0 0
x 0 0 1 1 x
x 0 1 0 1 x
OFF OFF OFF ON ON ON
OFF OFF ON OFF ON ON
PWDNB = 1
0 0 1
Rev. 1.1
19
S i4 13 3G
Control Registers
Table 10. Register Summary Register Name 0 1 2 3 4 5 6 . . . 15 Reserved Main Configuration Reserved Power Down RF1 N Divider RF2 N Divider IF N Divider Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDIB PDRB
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit 17 16 15 14 13 12 11 10 9 8 7 6 5 0 0 0 0
AUXSEL [1:0]
Bit 4 0
Bit 3
AUTO PDB
Bit 2 0
Bit 1 1
Bit 0 0
0
0
0
0
0
0
LPWR
NRF1[17:0] NRF[16:0] NIF[15:0]
Note: Registers 1 and 6-15 are reserved. Writes to these registers may result in unpredictable behavior. Any register not listed here is reserved and should not be written.
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SI4133G
Register 0. Main Configuration Address Field = A[3:0] = 0000 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 D9 0 0 0 0 AUXSEL [1:0] 0 0 0 D8 0 D7 0 D6 0 D5
LPWR
D4 0
D3
AUTO PDB
D2 0
D1 1
D0 0
Bit 17:14 13:12
Name Reserved AUXSEL [1:0] Program to zero.
Function
Auxiliary Output Pin Definition. 00 = Reserved. 01 = Force output low. 10 = Reserved. 11 = Lock Detect--LDETB. Program to zero. Output Power-Level Settings for IF Synthesizer Circuit. 0 = RLOAD < 500 --normal power mode. 1 = RLOAD 500 --low power mode. Program to zero. Auto Power Down 0 = Software powerdown is controlled by Register 2. 1 = Equivalent to setting all bits in Register 2 = 1. Program to zero. Program to one. Program to zero.
11:6 5
Reserved LPWR
4 3
Reserved AUTOPDB
2 1 0
Reserved Reserved Reserved
Rev. 1.1
21
S i4 13 3G
Register 2. Power Down Address Field (A[3:0]) = 0010 Bit Name Bit 17:2 1 D17 D16 D15 D14 D13 D12 D11 D10 D9 0 0 0 0 0 0 0 0 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1
PDIB
D0
PDRB
Name Reserved PDIB Program to zero.
Function
Power Down IF Synthesizer. 0 = IF synthesizer powered down. 1 = IF synthesizer on.
Note: Always program to 0 for Si4113G.
0
PDRB
Power Down RF Synthesizer. 0 = RF synthesizer powered down. 1 = RF synthesizer on.
Note: Always program to 0 for Si4112G.
Register 3. RF1 N Divider Address Field (A[3:0]) = 0011 Bit Name Bit 17:0 Name NRF1[17:0] D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NRF1[17:0] Function N Divider for RF1 Synthesizer. Register reserved for Si4112G, Si4122G. Writes to this register may result in unpredictable behavior.
22
Rev. 1.1
SI4133G
Register 4. RF2 N Divider Address Field = A[3:0] = 0100 Bit Name Bit 17 16:0 D17 D16 D15 D14 D13 D12 D11 D10 0 Name Reserved NRF2[16:0] Program to zero. N Divider for RF2 Synthesizer. Register reserved for Si4112G, Si4123G. Writes to this register may result in unpredictable behavior. D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NRF2[16:0] Function
Register 5. IF N Divider Address Field (A[3:0]) = 0101 Bit Name Bit 17:16 15:0 D17 D16 D15 D14 D13 D12 D11 D10 0 0 Name Reserved NIF[15:0] Program to zero. N Divider for IF Synthesizer. Register reserved for Si4113G. Writes to this register may result in unpredictable behavior. D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NIF[15:0] Function
Rev. 1.1
23
S i4 13 3G
Pin Descriptions: SI4133G-BT
SCLK S D ATA GNDR RFLD RFLC GNDR RFLB RFLA GNDR GNDR RFOU T VDDR
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
SEN B VDDI IF O U T GNDI IF L B IF L A GNDD VDDD GNDD X IN PWDNB AUXOUT
Pin Number(s) Name 1 2 3, 6, 9, 10 4, 5 7, 8 11 12 13 14 15 16, 18 17 19, 20 21 22 23 24 SCLK SDATA GNDR RFLC, RFLD RFLA, RFLB RFOUT VDDR AUXOUT PWDNB XIN GNDD VDDD IFLA, IFLB GNDI IFOUT VDDI SENB
Description Serial clock input Serial data input Common ground for RF analog circuitry Pins for inductor connection to RF2 VCO Pins for inductor connection to RF1 VCO Radio frequency (RF) output of the selected RF VCO Supply voltage for the RF analog circuitry Auxiliary output Power down input pin Reference frequency amplifier input Common ground for digital circuitry Supply voltage for digital circuitry Pins for inductor connection to IF VCO Common ground for IF analog circuitry Intermediate frequency (IF) output of the IF VCO Supply voltage for IF analog circuitry Enable serial port input
24
Rev. 1.1
SI4133G
Table 11. Pin Descriptions for SI4133G Derivatives--TSSOP
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SI4133G-BT Si4123G-BT Si4122G-BT Si4113G-BT SCLK SDATA GNDR RFLD RFLC GNDR RFLB RFLA GNDR GNDR RFOUT VDDR AUXOUT PWDNB XIN GNDD VDDD GNDD IFLA IFLB GNDI IFOUT VDDI SENB SCLK SDATA GNDR GNDR GNDR GNDR RFLB RFLA GNDR GNDR RFOUT VDDR AUXOUT PWDNB XIN GNDD VDDD GNDD IFLA IFLB GNDI IFOUT VDDI SENB SCLK SDATA GNDR RFLD RFLC GNDR GNDR GNDR GNDR GNDR RFOUT VDDR AUXOUT PWDNB XIN GNDD VDDD GNDD IFLA IFLB GNDI IFOUT VDDI SENB SCLK SDATA GNDR RFLD RFLC GNDR RFLB RFLA GNDR GNDR RFOUT VDDR AUXOUT PWDNB XIN GNDD VDDD GNDD GNDD GNDD GNDD GNDD VDDD SENB Si4112G-BT SCLK SDATA GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD VDDD AUXOUT PWDNB XIN GNDD VDDD GNDD IFLA IFLB GNDI IFOUT VDDI SENB
Rev. 1.1
25
S i4 13 3G
Pin Descriptions: SI4133G-BM
SDATA IFO UT
23
GN DR
SENB
SCLK
28
27
26
25
24
22 21 20 19 18 17 16 15
GNDR R FLD R FLC GNDR R FLB R FLA GNDR
1 2 3 4 5 6 7 8 9 10 11 12 13 14
GN DI
VDD I
GNDI IFLB IFLA GNDD VDDD GNDD X IN
R FO U T
AUX OU T
GN DR
GN DR
PW D NB
Pin Number(s) Name 1, 4, 7-9, 28 2, 3 5,6 10 11 12 13 14, 16, 18 15 17 19, 20 21, 22 23 24 25 26 27 GNDR RFLC, RFLD RFLA, RFLB RFOUT VDDR AUXOUT PWDNB GNDD XIN VDDD IFLA, IFLB GNDI IFOUT VDDI SENB SCLK SDATA
Description Common ground for RF analog circuitry Pins for inductor connection to RF2 VCO Pins for inductor connection to RF1 VCO Radio frequency (RF) output of the selected RF VCO Supply voltage for the RF analog circuitry Auxiliary output Power down input pin Common ground for digital circuitry Reference frequency amplifier input Supply voltage for digital circuitry Pins for inductor connection to IF VCO Common ground for IF analog circuitry Intermediate frequency (IF) output of the IF VCO Supply voltage for IF analog circuitry Enable serial port input Serial clock input Serial data input
26
Rev. 1.1
GN DD
VD DR
SI4133G
Table 12. Pin Descriptions for SI4133G Derivatives--MLP
Pin Number SI4133G-BM Si4123G-BM Si4122G-BM Si4113G-BM Si4112G-BM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 GNDR RFLD RFLC GNDR RFLB RFLA GNDR GNDR GNDR RFOUT VDDR AUXOUT PWDNB GNDD XIN GNDD VDDD GNDD IFLA IFLB GNDI GNDI IFOUT VDDI SENB SCLK SDATA GNDR GNDR GNDR GNDR GNDR RFLB RFLA GNDR GNDR GNDR RFOUT VDDR AUXOUT PWDNB GNDD XIN GNDD VDDD GNDD IFLA IFLB GNDI GNDI IFOUT VDDI SENB SCLK SDATA GNDR GNDR RFLD RFLC GNDR GNDR GNDR GNDR GNDR GNDR RFOUT VDDR AUXOUT PWDNB GNDD XIN GNDD VDDD GNDD IFLA IFLB GNDI GNDI IFOUT VDDI SENB SCLK SDATA GNDR GNDR RFLD RFLC GNDR RFLB RFLA GNDR GNDR GNDR RFOUT VDDR AUXOUT PWDNB GNDD XIN GNDD VDDD GNDD GNDD GNDD GNDD GNDD GNDD VDDD SENB SCLK SDATA GNDR GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD VDDD AUXOUT PWDNB GNDD XIN GNDD VDDD GNDD IFLA IFLB GNDI GNDI IFOUT VDDI SENB SCLK SDATA GNDD
Rev. 1.1
27
S i4 13 3G
Ordering Guide
Ordering Part Number SI4133G-BT* SI4133G-BM Si4123G-BT* Si4123G-BM Si4122G-BT* Si4122G-BM Si4113G-BT* Si4113G-BM Si4112G-BT* Si4112G-BM Description RF1/RF2/IF RF1/IF RF2/IF RF1/RF2 IF Operating Temperature -20 to 85oC -20 to 85oC -20 to 85oC -20 to 85oC -20 to 85oC
*Note: TSSOP not recommended for new designs.
SI4133G Derivative Devices
The SI4133G performs both IF and dual-band RF frequency synthesis. The Si4112G, Si4113G, Si4122G, and the Si4123G are derivatives of this device. Table 13 outlines which synthesizers each derivative device features as well as which pins and registers coincide with each synthesizer.
Table 13. SI4133G Derivatives
Name Si4112G Si4113G Si4122G Si4123G SI4133G Synthesizer IF RF1, RF2 RF2, IF RF1, IF RF1, RF2, IF Pins IFLA, IFLB RFLA, RFLB, RFLC, RFLD RFLC, RFLD, IFLA, IFLB RFLA, RFLB, IFLA, IFLB RFLA, RFLB, RFLC, RFLD, IFLA, IFLB Registers NIF, RIF, PDIB, IFDIV, LPWR, AUTOPDB = 0, PDRB = 0 NRF1, NRF2, RRF1, RRF2, PDRB, AUTOPDB = 0, PDIB = 0 NRF2, RRF2, PDRB, NIF, RIF, PDIB, LPWR NRF1, RRF1, PDRB, NIF, RIF, PDIB, LPWR NRF1, NRF2, RRF1, RRF2, PDRB, NIF, RIF, PDIB, LPWR
28
Rev. 1.1
SI4133G
Package Outline: SI4133G-BT
E1
E
2
R1 R
1
S
L L1
e
3
D
A2
A
c
b A1
Figure 19. 24-pin Thin Small Shrink Outline Package (TSSOP)
Table 14. Package Diagram Dimensions
Symbol A A1 A2 b c D e E E1 L L1 R R1 S 1 2 3 Min -- 0.05 0.80 0.19 0.09 7.70 Millimeters Nom 1.10 -- 1.00 -- -- 7.80 0.65 BSC 6.40 BSC 4.40 0.60 1.00 REF -- -- -- -- 12 REF 12 REF Max 1.20 0.15 1.05 0.30 0.20 7.90
4.30 0.45 0.09 0.09 0.20 0
4.50 0.75 -- -- -- 8
Rev. 1.1
29
S i4 13 3G
Package Outline: SI4133G-BM
Figure 20. 28-Pin Micro Leadframe Package (MLP) Table 15. Package Dimensions
Controlling Dimension: mm Symbol Min A A1 b D D1 E E1 N Nd Ne e L 0.50 -- 0.00 0.18 Millimeters Nom 0.90 0.01 0.23 5.00 BSC 4.75 BSC 5.00 BSC 4.75 BSC 28 7 7 0.50 BSC 0.60 0.75
12
Max 1.00 0.05 0.30
30
Rev. 1.1
SI4133G NOT E S :
Rev. 1.1
31
S i4 13 3G
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, Texas 78735 Tel:1+ (512) 416-8500 Fax:1+ (512) 416-9669 Toll Free:1+ (877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders.
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Rev. 1.1

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